1. Field of the Invention
The present invention relates to a dynamic-type semiconductor memory device and, more particularly, to an improvement of an arrangement of memory cells and a structure of electrical connections.
2. Description of the Prior Art
A dynamic-type semiconductor memory device is already well known. FIG. 1 is a block diagram showing an overall structure of a dynamic-type semiconductor memory device.
Referring to FIG. 1, a dynamic-type semiconductor memory device comprises an array comprising a plurality of memory cells serving as a memory portion, a X decoder and a Y decoder coupled to the memory portion for selecting its address, an input interface portion comprising a sense amplifier connected to the memory portion and an I/O buffer. A plurality of memory cells serving as a memory portion are provided as an array at intersection points of word lines connected to the X decoder and bit lines connected to the Y decoder structured as a matrix.
An operation is now described. In operation, upon receipt of a row address signal and a column address signal provided from outside, a memory cell at an intersection point of a single word line and a single bit line selected by the x decoder and Y decoder is selected, and information therein is read and written through the I/O interface portion comprising a sense amplifier and the I/O buffer.
FIG. 2 is an enlarged view showing intersection points of two word lines and a bit line of a conventional dynamic-type semiconductor device and showing that two memory cells are selected separately by two word lines and a bit line through a common contact hole provided in the center.
FIG. 3 is a sectional view taken along the line A--A in FIG. 2. Referring to FIGS. 2 and 3, a source region 6a and a drain region 6b of a transistor 6 are formed on a major surface of a silicon substrate 1 and a capacitor region 4a is provided adjacent to the drain region 6b. These regions ar isolated by an isolating region 7 and a channel cut 8 is formed under the isolating region 7. Word lines 3 are formed on a channel region 3a between the source region 6a and the drain region 6b through a gate insulating film 3b. Also, a capacitor electrode 9 is formed on the capacitor region 4a through a capacitor insulating film 4b. A plane region formed of the capacitor electrode 9 is shown by hatching of dotted lines in FIG. 2. These word lines 3 and the capacitor electrode 9 are covered with an insulating layer 10. A bit line 5 formed on the insulating layer 10 is connected to the source region 6a common to the two transistors 6. That is, two capacitor regions 4a are connected to a single bit line 5 by one contact hole 2 through respective switching transistor 6.
As mentioned above, according to the conventional dynamic-type semiconductor memory device, since two memory cells are connected to a bit line through a single contact hole, contact holes as many as a half of the number of storage bits are necessary. Therefore, problems were caused that a high degree of integration of semiconductor memory device is difficult due to the region occupied by these many contact holes.